- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.8-$3.6
更新日期:2024-04-01 00:04:00
产品简介:具有三态输出的 3.3V ABT 18 位通用总线收发器
查看详情- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.8-$3.6
SN74LVT16501DGGR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
TSSOP
23+ -
46000
-
合肥
-
-
-
科大讯飞战略投资企业,提供一站式配套服务
SN74LVT16501DGGR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 通用总线函数
- 系列:74LVT
- 逻辑类型:通用总线收发器
- 输入数:-
- 电路数:18 位
- 输出电流高,低:32mA,64mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-TFSOP(0.240",6.10mm 宽)
- 供应商设备封装:56-TSSOP
- 包装:®
- 其它名称:296-1252-6
产品特性
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation
- Members of the Texas Instruments WidebusTM Family
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Support Live Insertion
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
产品概述
The 'LVT16501 are 18-bit universal bus transceivers designed for
low-voltage (3.3-V) VCC operation, but with the capability
to provide a TTL interface to a 5-V system environment.Data flow in each direction is controlled by output-enable (OEAB
and ), latch-enable
(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data
flow, the devices operate in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at a high or
low logic level. If LEAB is low, the A-bus data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is
high, the outputs are active. When OEAB is low, the outputs are in
the high-impedance state. Data flow for B to A is similar to that of A to B but uses , LEBA, and CLKBA. The output
enables are complementary (OEAB is active high and is active low).Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor. The minimum value of the
resistor is determined by the current-sinking capability of the
driver. OE should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sourcing
capability of the driver.The SN74LVT16501 is available in TI's shrink small-outline (DL)
and thin shrink small-outline (DGG) packages, which provide twice the
input/output (I/O) pin count and functionality of standard
small-outline packages in the same printed circuit board area.The SN54LVT16501 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74LVT16501 is characterized for operation from -40°C to
85°C.
SN74LVT16501DGGR 数据手册
| 数据手册 | 说明 | 数量 | 操作 |
|---|---|---|---|
SN74LVT16501DGGR
|
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
12 Pages页,204K | 查看 |
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