- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.5984-$3.2
更新日期:2024-04-01 00:04:00
产品简介:具有三态输出的 3.3V ABT 16 位寄存收发器
查看详情- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.5984-$3.2
SN74LVT16952DGGR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-56
2022+ -
12000
-
上海市
-
-
-
原装可开发票
SN74LVT16952DGGR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74LVT
- 逻辑类型:寄存收发器,非反相
- 元件数:2
- 每个元件的位元数:8
- 输出电流高,低:32mA,64mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-TFSOP(0.240",6.10mm 宽)
- 供应商设备封装:56-TSSOP
- 包装:®
- 其它名称:296-1253-6
产品特性
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation
- Members of the Texas Instruments WidebusTM Family
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
- Support Live Insertion
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings Widebus is a trademark of Texas Instruments Incorporated.
产品概述
The 'LVT16952 are 16-bit registered transceivers designed for
low-voltage (3.3-V) VCC operation, but with the capability
to provide a TTL interface to a 5-V system environment. These devices
can be used as two 8-bit transceivers or one 16-bit transceiver. Data
on the A or B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the
clock-enable (or ) input is low. Taking the
output-enable ( or ) input low accesses the data on
either port.Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.The SN74LVT16952 is available in TI's shrink small-outline (DL)
and thin shrink small-outline (DGG) packages, which provide twice the
I/O pin count and functionality of standard small-outline packages in
the same printed-circuit-board area. The SN54LVT16952 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74LVT16952 is characterized for operation from -40°C to
85°C.
SN74LVT16952DGGR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
11 Pages页,195K | 查看 |
SN74LVT16952DGGR 相关产品
- 100314QC
- 1P1G125QDCKRG4Q1
- 1P1G125QDCKRQ1
- 1P1G126QDBVRQ1
- 74ABT125PW,118
- 74ABT162244CSSX
- 74ABT162244DGGRG4
- 74ABT162245DLRG4
- 74ABT16245ADGGRG4
- 74ABT244D,623
- 74ABT245PW,118
- 74AC11244DBR
- 74AC11244DWR
- 74AC11244PWR
- 74AC11245DW
- 74AC11245DWR
- 74AC16244DGGR
- 74AC16244DL
- 74AC16244DLR
- 74AC16245DLR
- 74AC16652DL
- 74ACT11244DBR
- 74ACT11244DWR
- 74ACT11244PWR
- 74ACT11245DBR
- 74ACT11245DWR
- 74ACT11245NSR
- 74ACT11245PWR
- 74ACT16244DGGR
- 74ACT16244DLR