- 封装:24-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.406
更新日期:2024-04-01 00:04:00
产品简介:具有 TTL 兼容型 CMOS 输入的 10 通道、2V 至 5.5V 缓冲器
查看详情- 封装:24-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.406
SN74LV8151PWRE4 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
SN74LV8151PWRE4 中文资料属性参数
- 标准包装:2,000
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74LV
- 逻辑类型:施密特触发器 - 缓冲器,驱动器
- 元件数:1
- 每个元件的位元数:8
- 输出电流高,低:12mA,12mA
- 电源电压:2 V ~ 5.5 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:24-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:24-TSSOP
- 包装:带卷 (TR)
产品特性
- 2-V to 5.5-V VCC Operation
- Max tpd of 15 ns at 5 V
- Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time
- Polarity Control for Y Outputs Selects True or Complementary Logic
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >>2.3 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Supports Mixed-Mode Voltage Operation on All Ports
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCC operation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic).When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74LV8151PWRE4 相关产品
- 100314QC
- 1P1G125QDCKRG4Q1
- 1P1G125QDCKRQ1
- 1P1G126QDBVRQ1
- 74ABT125PW,118
- 74ABT162244CSSX
- 74ABT162244DGGRG4
- 74ABT162245DLRG4
- 74ABT16245ADGGRG4
- 74ABT244D,623
- 74ABT245PW,118
- 74AC11244DBR
- 74AC11244DWR
- 74AC11244PWR
- 74AC11245DW
- 74AC11245DWR
- 74AC16244DGGR
- 74AC16244DL
- 74AC16244DLR
- 74AC16245DLR
- 74AC16652DL
- 74ACT11244DBR
- 74ACT11244DWR
- 74ACT11244PWR
- 74ACT11245DBR
- 74ACT11245DWR
- 74ACT11245NSR
- 74ACT11245PWR
- 74ACT16244DGGR
- 74ACT16244DLR