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  • 封装:16-SOIC(0.209",5.30mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)

更新日期:2024-04-01 00:04:00

产品简介:IC SERIAL-IN SHIFT-REG 16-SOP

  • 封装:16-SOIC(0.209",5.30mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)

SN74LS594NSR 供应商

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  • 说明
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SN74LS594NSR 中文资料属性参数

  • 标准包装:2,000
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 移位寄存器
  • 系列:74LS
  • 逻辑类型:移位寄存器
  • 输出类型:标准
  • 元件数:1
  • 每个元件的位元数:8
  • 功能:串行至并行
  • 电源电压:4.75 V ~ 5.25 V
  • 工作温度:0°C ~ 70°C
  • 安装类型:表面贴装
  • 封装/外壳:16-SOIC(0.209",5.30mm 宽)
  • 供应商设备封装:16-SO
  • 包装:带卷 (TR)

SN74LS594NSR 数据手册

数据手册 说明 数量 操作
SN74LS594NSR

These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.

7页,349K 查看
SN74LS594NSRE4

These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.

7页,349K 查看
SN74LS594NSRG4

These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.

7页,349K 查看

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