- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
更新日期:2024-04-01
产品简介:CMOS 双路 4 级静态移位寄存器
查看详情- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
CD4015BPWR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-16
2022+ -
3681
-
上海市
-
-
-
原装可开发票
-
TI
-
-
2021+ -
28000
-
苏州
-
-
CD4015BPWR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:4000B
- 逻辑类型:移位寄存器
- 输出类型:标准
- 元件数:2
- 每个元件的位元数:4
- 功能:串行至并行
- 电源电压:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:16-TSSOP
- 包装:®
- 其它名称:296-14090-6
产品特性
- Medium speed operation...12 MHz (typ.) clock rate at VDD VSS = 10 V
- Fully static operation
- 8 master-slave flip-flops plus input and output buffering
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications: Serial-input/parallel-output data queueing Serial to parallel data conversion General-purpose register
- Serial-input/parallel-output data queueing
- Serial to parallel data conversion
- General-purpose register
产品概述
CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers.
Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q"
outputs are available from each of the four stages on both registers. All register stages are D-type,
master-slave flip-flops. The logic level present at the DATA input is transferred into the first
register stage and shifted over one stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one
CD4015B package, or to more than 8 stages using additional CD4015Bs is possible.The CD4015B-series types are supplied in
16-lead hermetic dual-in-line ceramic
packages (F3A suffix), 16-lead dual-in-line
plastic package (E suffix), 16-lead
small-outline packages (M, M96, MT, and NSR
suffixes), and 16-lead thin shrink small-outline
packages (PW and PWR suffixes).
CD4015BPWR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
CMOS Dual 4-Stage Static Shift Register 16-TSSOP -55 to 125 |
14页,687K | 查看 |
![]() |
CMOS Dual 4-Stage Static Shift Register 16-TSSOP -55 to 125 |
14页,687K | 查看 |
![]() |
CMOS Dual 4-Stage Static Shift Register 16-TSSOP -55 to 125 |
14页,687K | 查看 |
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