- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$11.94-$21.89
更新日期:2024-04-01 00:04:00
产品简介:具有输出锁存器的串行输入移位寄存器
查看详情- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$11.94-$21.89
SN74LS594N 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
SN74LS594N 中文资料属性参数
- 标准包装:25
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:74LS
- 逻辑类型:移位寄存器
- 输出类型:标准
- 元件数:1
- 每个元件的位元数:8
- 功能:串行至并行
- 电源电压:4.75 V ~ 5.25 V
- 工作温度:0°C ~ 70°C
- 安装类型:通孔
- 封装/外壳:16-DIP(0.300",7.62mm)
- 供应商设备封装:16-PDIP
- 包装:管件
- 其它名称:296-3720-5
产品特性
- 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
- Choice of Output Configurations: 'LS594 . . . Buffered 'LS599 . . . Open-Collector
- Guaranteed Shift Frequeny: DC to 20 MHz
- Independent Direct-Overriding Clears on Shift and Storage Registers
产品概述
SN74LS594N 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
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Serial-in shift registers with output latches 16-PDIP 0 to 70 |
7页,349K | 查看 |
![]() |
IC SERIAL-IN SHIFT-REG 16-DIP |
7页,391K | 查看 |
![]() |
Serial-in shift registers with output latches 16-PDIP 0 to 70 |
7页,349K | 查看 |
![]() |
These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register. |
7页,349K | 查看 |
![]() |
These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register. |
7页,349K | 查看 |
![]() |
These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register. |
7页,349K | 查看 |
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