- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.5115-$1.19
更新日期:2024-04-01 00:04:00
产品简介:8 位并行负载移位寄存器(增强型产品)
查看详情- 封装:16-TSSOP(0.173",4.40mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.5115-$1.19
SN74HC165QPWREP 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
SN74HC165QPWREP 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:74HC
- 逻辑类型:移位寄存器
- 输出类型:差分
- 元件数:1
- 每个元件的位元数:8
- 功能:并行或串行至串行
- 电源电压:2 V ~ 6 V
- 工作温度:-40°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:16-TSSOP
- 包装:®
- 其它名称:296-22298-6
产品特性
- Controlled Baseline One Assembly/Test Site, One Fabrication Site
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of Up To 55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- 2-V to 6-V VCC Operation
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 13 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
产品概述
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. While SH/LD\ is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
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