SN74HC164DR

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1-µA Maximum
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

产品概述

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

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SN74HC164DR 数据手册

数据手册	说明	数量	操作
SN74HC164DR	8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85	18页,704K	查看
SN74HC164DRE4	8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85	18页,704K	查看
SN74HC164DRG3	IC SHIFT REGISTER 8BIT 14SOIC	33页,1.18M	查看
SN74HC164DRG4	8-Bit Parallel-Out Serial Shift Registers 14-SOIC -40 to 85	18页,704K	查看

SN74HC164DR 电路图

IC 索引： A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9

SN74HC164DR

SN74HC164DR

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SN74HC164DR 中文资料属性参数

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产品概述

SN74HC164DR 数据手册

SN74HC164DR 电路图

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