SN74AUC125RGYR

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V to 1.95-V VCC operation.The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.