- 封装:56-BSSOP(0.295",7.50mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
更新日期:2024-04-01 00:04:00
产品简介:IC 64X18 SYNC FIFO MEM 56-SSOP
- 封装:56-BSSOP(0.295",7.50mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
SN74ALVC7813-20DLR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
SN74ALVC7813-20DLR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - FIFO
- 系列:74ALVC
- 功能:同步
- 存储容量:1.1K(64 x 18)
- 数据速率:50MHz
- 访问时间:-
- 电源电压:3 V ~ 3.6 V
- 工作温度:0°C ~ 70°C
- 安装类型:表面贴装
- 封装/外壳:56-BSSOP(0.295",7.50mm 宽)
- 供应商设备封装:56-SSOP
- 包装:Digi-Reel®
- 其它名称:296-15980-6
SN74ALVC7813-20DLR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
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The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is hi... |
16页,231K | 查看 |
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