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  • 封装:28-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$3.69-$7.5

更新日期:2024-04-01

产品简介:256 x 1 x 2 双独立同步 FIFO 存储器

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  • 封装:28-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$3.69-$7.5

SN74ACT2229DW 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN74ACT2229DW 中文资料属性参数

  • 标准包装:20
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - FIFO
  • 系列:74ACT
  • 功能:同步
  • 存储容量:256(256 x 1)
  • 数据速率:60MHz
  • 访问时间:-
  • 电源电压:4.5 V ~ 5.5 V
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:28-SOIC(0.295",7.50mm 宽)
  • 供应商设备封装:28-SOIC
  • 包装:管件
  • 其它名称:296-4373-5

产品特性

  • Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each - SN74ACT2227 256 Words by 1 Bit Each - SN74ACT2229
  • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO
  • Input-Ready Flags Synchronized to Write Clocks
  • Output-Ready Flags Synchronized to Read Clocks
  • Half-Full and Almost-Full/Almost-Empty Flags
  • Support Clock Frequencies up to 60 MHz
  • Access Times of 9 ns
  • 3-State Data Outputs
  • Low-Power Advanced CMOS Technology
  • Packaged in 28-Pin SOIC Package

产品概述

The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering applications including elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE). Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the high-impedance state when its output-enable (1OE or 2OE) input is low. Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously. A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO. The SN74ACT2227 and SN74ACT2229 are characterized for operation from -40°C to 85°C. For more information on this device family, see the application report FIFOs With a Word Width of One Bit (literature number SCAA006).

SN74ACT2229DW 数据手册

数据手册 说明 数量 操作
SN74ACT2229DW

256 x 1 x 2 dual independent synchronous FIFO memories 28-SOIC -40 to 85

15页,279K 查看
SN74ACT2229DW

IC DUAL 256 X 1 FIFO MEM 28-SOIC

18页,782K 查看
SN74ACT2229DWR

256 x 1 x 2 dual independent synchronous FIFO memories 28-SOIC -40 to 85

15页,279K 查看

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