- 封装:56-BSSOP(0.295",7.50mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$3.075
更新日期:2024-04-01 00:04:00
产品简介:具有奇偶校验发生器/校验器和三态输出的 16 位收发器
查看详情- 封装:56-BSSOP(0.295",7.50mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$3.075
SN74ABT16657DL 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
SSOP56
23+ -
15000
-
上海市
-
-
-
中国区代理原装进口特价
-
TI(德州仪器)
-
SSOP-56
2022+ -
12000
-
上海市
-
-
-
原装可开发票
SN74ABT16657DL 中文资料属性参数
- 标准包装:20
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74ABT
- 逻辑类型:收发器,非反相
- 元件数:2
- 每个元件的位元数:8
- 输出电流高,低:32mA,64mA
- 电源电压:4.5 V ~ 5.5 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-BSSOP(0.295",7.50mm 宽)
- 供应商设备封装:56-SSOP
- 包装:管件
产品特性
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
产品概述
The 'ABT16657 contain two noninverting octal transceiver sections
with separate parity generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R\ or 2T/R\) input
determines the direction of data flow. When 1T/R\ (or 2T/R\) is high,
data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R\ (or 2T/R\) is low, data flows from the 1B (or 2B)
port to the 1A (or 2A) port (receive mode). When the output-enable
(1 or 2) input is high, both the 1A (or
2A) and 1B (or 2B) ports are in the high-impedance state.Odd or even parity is selected by a logic high or low level,
respectively, on the 1ODD (or
2ODD) input.
1PARITY (or 2PARITY) carries the parity bit value; it is an output
from the parity generator/checker in the transmit mode and an input
to the parity generator/checker in the receive mode.In the transmit mode, after the 1A (or 2A) bus is polled to
determine the number of high bits, 1PARITY (or 2PARITY) is set to the
logic level that maintains the parity sense selected by the level at
the 1ODD (or 2ODD) input. For example, if 1ODD is low (even parity selected) and
there are five high bits on the 1A bus, then 1PARITY is set to the
logic high level so that an even number of the nine total bits (eight
1A-bus bits plus parity bit) are high. In the receive mode, after the 1B (or 2B) bus is polled to
determine the number of high bits, the 1(or 2) output logic level indicates
whether or not the data to be received exhibits the correct parity
sense. For example, if 1ODD is
high (odd parity selected), 1PARITY is high, and there are three high
bits on the 1B bus, then 1 is
low, indicating a parity error.To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.The SN54ABT16657 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74ABT16657 is characterized for operation from -40°C to
85°C.
SN74ABT16657DL 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
10 Pages页,184K | 查看 |
![]() |
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
10 Pages页,184K | 查看 |
![]() |
Transceiver, Non-Inverting 2 Element 8 Bit per Element Push-Pull Output 56-SSOP |
12页,355K | 查看 |
![]() |
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS |
10 Pages页,184K | 查看 |
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