- 封装:8-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$1.902
更新日期:2024-04-01
产品简介:1.5Gbps LVDS/LVPECL/CML 至 CML 转换器/中继器
查看详情- 封装:8-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$1.902
SN65CML100DR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI/德州仪器
-
SOP8
21+ -
10000
-
杭州
-
-
-
只做原装现货,大量现货热卖
SN65CML100DR 中文资料属性参数
- 标准包装:2,500
- 类别:集成电路 (IC)
- 家庭:逻辑 - 变换器
- 系列:65CML
- 逻辑功能:变换器
- 位数:1
- 输入类型:CML,LVDS,LVPECL
- 输出类型:CML
- 数据速率:-
- 通道数:1
- 输出/通道数目:1
- 差分 - 输入:输出:无/无
- 传输延迟(最大):0.8ns
- 电源电压:3 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 封装/外壳:8-SOIC(0.154",3.90mm 宽)
- 供应商设备封装:8-SOIC
- 包装:带卷 (TR)
- 配用:296-20537-ND - EVAL MOD FOR SN65CML100DGK
产品特性
- Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
- Signaling Rates1 up to 1.5 Gbps
- CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
- Total Jitter < 70 ps
- Low 100 ps (Max) Part-To-Part Skew
- Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
- 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
- Propagation Delay Times, 800 ps Maximum
- 3.3-V Supply Operation
- Available in SOIC and MSOP Packages
- APPLICATIONS Level Translation 622-MHz Central Office Clock Distribution High-Speed Network Routing Wireless Basestations Low Jitter Clock Repeater
- Level Translation
- 622-MHz Central Office Clock Distribution
- High-Speed Network Routing
- Wireless Basestations
- Low Jitter Clock Repeater
产品概述
This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.This device is characterized for operation from 40°C to 85°C.
SN65CML100DR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater 8-SOIC -40 to 85 |
26页,574K | 查看 |
![]() |
1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater 8-SOIC -40 to 85 |
26页,574K | 查看 |
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