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  • 封装:48-TFSOP(0.240",6.10mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.489

更新日期:2024-04-01

产品简介:具有三态输出的 16 位 2.5V 至 3.3V/3.3V 至 5V 电平转换收发器

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  • 封装:48-TFSOP(0.240",6.10mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:带卷 (TR)
  • 参考价格:$0.489

74ALVC164245DGGRG4 供应商

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74ALVC164245DGGRG4 中文资料属性参数

  • 标准包装:2,000
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 变换器
  • 系列:74ALVC
  • 逻辑功能:电平移位器,3 态
  • 位数:16
  • 输入类型:逻辑
  • 输出类型:逻辑
  • 数据速率:-
  • 通道数:16
  • 输出/通道数目:1
  • 差分 - 输入:输出:无/无
  • 传输延迟(最大):5.8ns
  • 电源电压:2.3 V ~ 3.6 V ~ 3 V ~ 5.5 V
  • 工作温度:-40°C ~ 85°C
  • 封装/外壳:48-TFSOP(0.240",6.10mm 宽)
  • 供应商设备封装:48-TSSOP
  • 包装:带卷 (TR)

产品特性

  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS Electronic Points of Sale Printers and Other Peripherals Motor Drives Wireless and Telecom Infrastructures Wearable Health and Fitness Devices
  • Electronic Points of Sale
  • Printers and Other Peripherals
  • Motor Drives
  • Wireless and Telecom Infrastructures
  • Wearable Health and Fitness Devices

产品概述

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

74ALVC164245DGGRG4 电路图

74ALVC164245DGGRG4 电路图

74ALVC164245DGGRG4 电路图

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