- 封装:48-TSSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.341-$2.87
更新日期:2024-04-01 00:04:00
产品简介:具有总线保持、TTL 兼容型 CMOS 输入和三态输出的增强型产品 16 通道、2.7V 至 3.6V 缓冲器
查看详情- 封装:48-TSSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$1.341-$2.87
CLVTH162244IDGGREP 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-48
2022+ -
12000
-
上海市
-
-
-
原装可开发票
CLVTH162244IDGGREP 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74LVTH
- 逻辑类型:缓冲器/线路驱动器,非反相
- 元件数:4
- 每个元件的位元数:4
- 输出电流高,低:12mA,12mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:48-TSSOP(0.240",6.10mm 宽)
- 供应商设备封装:48-TSSOP
- 包装:®
- 其它名称:296-22117-6
产品特性
- Controlled Baseline One Assembly/Test Site, One Fabrication Site
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Member of the Texas Instruments Widebus Family
- Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
- Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Supports Unregulated Battery Operation Down To 2.7 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Ioff and Power-Up 3-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
The SN74LVTH162244 is a 16-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides true outputs and symmetrical active-low output-enable (OE)\ inputs.The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
CLVTH162244IDGGREP 数据手册
| 数据手册 | 说明 | 数量 | 操作 |
|---|---|---|---|
CLVTH162244IDGGREP
|
Buffer, Non-Inverting 4 Element 4 Bit per Element Push-Pull Output 48-TSSOP |
10页,293K | 查看 |
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