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  • 封装:24-SSOP(0.209",5.30mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$10.108-$9.728

更新日期:2024-04-01

产品简介:具有三态输出的 1 线至 10 线 3.3V 时钟驱动器

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  • 封装:24-SSOP(0.209",5.30mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$10.108-$9.728

CDC351IDB 供应商

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  • 封装/批号
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  • 说明
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CDC351IDB 中文资料属性参数

  • 标准包装:60
  • 类别:集成电路 (IC)
  • 家庭:时钟/计时 - 时钟缓冲器,驱动器
  • 系列:-
  • 类型:扇出缓冲器(分配)
  • 电路数:1
  • 比率 - 输入:输出:1:10
  • 差分 - 输入:输出:无/无
  • 输入:LVTTL
  • 输出:LVTTL,三态
  • 频率 - 最大:100MHz
  • 电源电压:3 V ~ 3.6 V
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:24-SSOP(0.209",5.30mm 宽)
  • 供应商设备封装:24-SSOP
  • 包装:管件
  • 其它名称:296-15849-5

产品特性

  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to Ten Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-32-mA IOH, 32-mA IOL)
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

产品概述

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

CDC351IDB 数据手册

数据手册 说明 数量 操作
CDC351IDB

Clock Fanout Buffer (Distribution) IC 100MHz 24-SSOP (0.209", 5.30mm Width)

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