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CD74HC194PWR

Texas Instruments 逻辑 - 移位寄存器
  • 封装：16-TSSOP（0.173"，4.40mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：Digi-Reel®
  • 参考价格：$0.2275-$0.64

更新日期：2024-04-01

CD74HC194PWR

Texas Instruments 逻辑 - 移位寄存器

产品简介：高速 CMOS 逻辑 4 位双向通用移位寄存器

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  • 封装：16-TSSOP（0.173"，4.40mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：Digi-Reel®
  • 参考价格：$0.2275-$0.64

CD74HC194PWR 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD74HC194PWR 中文资料属性参数

  • 标准包装：1
  • 类别：集成电路 (IC)
  • 家庭：逻辑 - 移位寄存器
  • 系列：74HC
  • 逻辑类型：双向寄存器
  • 输出类型：标准
  • 元件数：1
  • 每个元件的位元数：4
  • 功能：通用
  • 电源电压：2 V ~ 6 V
  • 工作温度：-55°C ~ 125°C
  • 安装类型：表面贴装
  • 封装/外壳：16-TSSOP（0.173"，4.40mm 宽）
  • 供应商设备封装：16-TSSOP
  • 包装：®
  • 其它名称：296-12794-6

产品特性

  • Four Operating Modes Shift Right, Shift Left, Hold and Reset
  • Shift Right, Shift Left, Hold and Reset
  • Synchronous Parallel or Serial Operation
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Asynchronous Master Reset
  • Fanout (Over Temperature Range) Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

产品概述

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.
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CD74HC194PWR 数据手册

数据手册 说明 数量 操作
CD74HC194PWR

High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

 13 Pages页,340K 查看
CD74HC194PWR

IC SHFT REGSTR UNIV BIDIR16TSSOP

 18页,899K 查看
CD74HC194PWRG4

High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register 16-TSSOP -55 to 125

17页,527K 查看

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