您好,欢迎来到知芯网
  • 封装:*
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:*
  • 参考价格:$0.2275-$0.64

更新日期:2024-04-01 00:04:00

产品简介:高速 CMOS 逻辑 10 线至 4 线优先级编码器

查看详情
  • 封装:*
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:*
  • 参考价格:$0.2275-$0.64

CD74HC147PWR 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD74HC147PWR 中文资料属性参数

  • 标准包装:1
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 信号开关,多路复用器,解码器
  • 系列:74HC
  • 类型:优先顺序编码器
  • 电路:1 x 10:4
  • 独立电路:1
  • 输出电流高,低:5.2mA,5.2mA
  • 电压电源:单电源
  • 电源电压:2 V ~ 6 V
  • 工作温度:-55°C ~ 125°C
  • 安装类型:*
  • 封装/外壳:*
  • 供应商设备封装:*
  • 包装:*
  • 其它名称:296-31566-6

产品特性

  • Buffered Inputs and Outputs
  • Typical Propagation Delay: 13ns at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range) Standard Outputs...10 LSTTL Loads Bus Driver Outputs...15 LSTTL Loads
  • Standard Outputs...10 LSTTL Loads
  • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

产品概述

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l1 to l9) and provide binary representation on the four active LOW inputs (Y0\ to Y3\). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l9 having the highest priority.These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

CD74HC147PWR 数据手册

数据手册 说明 数量 操作
CD74HC147PWR

High-Speed CMOS Logic 10- to 4-Line Priority Encoder

13 Pages页,349K 查看
CD74HC147PWR

Priority Encoder 1 x 10:4 16-TSSOP

17页,680K 查看
CD74HC147PWRE4

High-Speed CMOS Logic 10- to 4-Line Priority Encoder

13 Pages页,344K 查看

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9