- 封装:16-SOIC(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
更新日期:2024-04-01
产品简介:CMOS 8 级移位存储总线寄存器
查看详情- 封装:16-SOIC(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.1785-$0.5
CD4094BNSR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
SOP-16/中体
- -
16321
-
上海市
-
-
-
经营22年实体店原装,具体年份和数量以实际为准
-
TI
-
-
8 -
4000
-
杭州
-
-
-
原装正品现货
-
TI(德州仪器)
-
SOIC-16_208mil
2022+ -
12000
-
上海市
-
-
-
原装可开发票
CD4094BNSR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:4000B
- 逻辑类型:移位寄存器
- 输出类型:三态
- 元件数:1
- 每个元件的位元数:8
- 功能:串行至并行
- 电源电压:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-SOIC(0.209",5.30mm 宽)
- 供应商设备封装:16-SO
- 包装:®
- 其它名称:296-27189-6
产品特性
- 3-state parallel outputs for connection to common bus
- Separate serial outputs synchronous to both positive and negative clock edges for cascading
- Medium speed operation - 5 MHz at 10 V (typ.)
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications Serial-to-parallel data conversion Remote control holding register Dual-rank shift, hold, and bus applications
- Serial-to-parallel data conversion
- Remote control holding register
- Dual-rank shift, hold, and bus applications
产品概述
CD4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.Two serial outputs are available for cascading a number of CD4094B devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q'S terminal on the next negative clock edge, provides a means for cascading CD4094B devices when the clock rise time is slow.The CD4094B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4094BNSR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
CMOS 8-Stage Shift-and-Store Bus Register 16-SO -55 to 125 |
13页,693K | 查看 |
![]() |
CMOS 8-Stage Shift-and-Store Bus Register 16-SO -55 to 125 |
13页,693K | 查看 |
![]() |
CMOS 8-Stage Shift-and-Store Bus Register 16-SO -55 to 125 |
13页,693K | 查看 |
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