- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$0.49664-$1.36
更新日期:2024-04-01 00:04:00
产品简介:CMOS 4 级并行输入/并行输出移位寄存器
查看详情- 封装:16-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$0.49664-$1.36
CD4035BE 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
PDIP-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
CD4035BE 中文资料属性参数
- 标准包装:25
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:4000B
- 逻辑类型:移位寄存器
- 输出类型:差分
- 元件数:1
- 每个元件的位元数:4
- 功能:并行或串行至串行
- 电源电压:3 V ~ 18 V
- 工作温度:-55°C ~ 125°C
- 安装类型:通孔
- 封装/外壳:16-DIP(0.300",7.62mm)
- 供应商设备封装:16-PDIP
- 包装:管件
- 其它名称:296-2163-5
产品特性
- 4-Stage clocked shift operation
- Synchronous parallel entry on all 4 stages
- JK\ inputs on first stage
- Asynchronous True/Complement control on all outputs
- Static flip-flop operation; Master-slave configuration
- Buffered inputs and outputs
- High speed 12 MHz (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications: Counters, Registers Arithmetic-unit registers Shift-left shift right registers Serial-to-parallel/parallel-to-serial conversions Sequence generation Control circuits Code conversion
- Counters, Registers Arithmetic-unit registers Shift-left shift right registers Serial-to-parallel/parallel-to-serial conversions
- Arithmetic-unit registers
- Shift-left shift right registers
- Serial-to-parallel/parallel-to-serial conversions
- Sequence generation
- Control circuits
- Code conversion
产品概述
CD4035B is a four-stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK\ logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERIAL control low).Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high.In the parallel or serial mode information is transferred on positive clock transitions.When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. THe TRUE/COMPLEMENT control functions asynchronously with respect to the CLOCK signal.JK\ input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. With JK\ inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided.The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4035BE 数据手册
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CD4035BE