- 封装:48-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.648
更新日期:2024-04-01
产品简介:具有三态输出的 3.3V ABT 16 位总线收发器
查看详情- 封装:48-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:带卷 (TR)
- 参考价格:$0.648
74LVT16245BDGGRE4 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
74LVT16245BDGGRE4 中文资料属性参数
- 标准包装:2,000
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74LVT
- 逻辑类型:收发器,非反相
- 元件数:2
- 每个元件的位元数:8
- 输出电流高,低:32mA,32mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:48-TFSOP(0.240",6.10mm 宽)
- 供应商设备封装:48-TSSOP
- 包装:带卷 (TR)
产品特性
- Member of the Texas Instruments Widebus Family
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Ioff and Power-Up 3-State Support Hot Insertion
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
The 'LVT16245B devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.These devices are designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
74LVT16245BDGGRE4 相关产品
- 100314QC
- 1P1G125QDCKRG4Q1
- 1P1G125QDCKRQ1
- 1P1G126QDBVRQ1
- 74ABT125PW,118
- 74ABT162244CSSX
- 74ABT162244DGGRG4
- 74ABT162245DLRG4
- 74ABT16245ADGGRG4
- 74ABT244D,623
- 74ABT245PW,118
- 74AC11244DBR
- 74AC11244DWR
- 74AC11244PWR
- 74AC11245DW
- 74AC11245DWR
- 74AC16244DGGR
- 74AC16244DL
- 74AC16244DLR
- 74AC16245DLR
- 74AC16652DL
- 74ACT11244DBR
- 74ACT11244DWR
- 74ACT11244PWR
- 74ACT11245DBR
- 74ACT11245DWR
- 74ACT11245NSR
- 74ACT11245PWR
- 74ACT16244DGGR
- 74ACT16244DLR