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  • 封装:20-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$1.192-$2.55

更新日期:2024-04-01 00:04:00

产品简介:具有三态输出的 3.3V ABT 八路边沿 D 类触发器

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  • 封装:20-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$1.192-$2.55

SN74LVT574PWR 供应商

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SN74LVT574PWR 中文资料属性参数

  • 标准包装:1
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 触发器
  • 系列:74LVT
  • 功能:标准
  • 类型:D 型总线
  • 输出类型:三态非反相
  • 元件数:1
  • 每个元件的位元数:8
  • 频率 - 时钟:150MHz
  • 延迟时间 - 传输:3.6ns
  • 触发器类型:正边沿
  • 输出电流高,低:32mA,64mA
  • 电源电压:2.7 V ~ 3.6 V
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:20-TSSOP(0.173",4.40mm 宽)
  • 包装:®
  • 其它名称:296-1257-6

产品特性

  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°C
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model(C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
  • Support Live Insertion
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Packages, and Ceramic (J) DIPs

产品概述

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.The eight flip-flops of the ´LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.To ensure the high-impedance state during power up or power down, should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.The SN74LVT574 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.The SN54LVT574 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT574 is characterized for operation from -40°C to 85°C.  

SN74LVT574PWR 数据手册

数据手册 说明 数量 操作
SN74LVT574PWR

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

16 Pages页,471K 查看
SN74LVT574PWRE4

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

16 Pages页,442K 查看

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