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  • 封装:20-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$0.558-$1.3

更新日期:2024-04-01 00:04:00

产品简介:增强型产品,具有三态输出的八路 D 类透明锁存器

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  • 封装:20-TSSOP(0.173",4.40mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:Digi-Reel®
  • 参考价格:$0.558-$1.3

SN74LVC373AQPWREP 供应商

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SN74LVC373AQPWREP 中文资料属性参数

  • 标准包装:1
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 锁销
  • 系列:74LVC
  • 逻辑类型:D 型透明锁存器
  • 电路:8:8
  • 输出类型:三态
  • 电源电压:1.65 V ~ 3.6 V
  • 独立电路:1
  • 延迟时间 - 传输:1.5ns
  • 输出电流高,低:24mA,24mA
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:20-TSSOP(0.173",4.40mm 宽)
  • 供应商设备封装:20-TSSOP
  • 包装:®
  • 其它名称:296-22366-6

产品特性

  • Controlled BaselineOne Assembly/Test Site, One Fabrication Site
  • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Operates From 2 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.5 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation

产品概述

The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.The SN74LVC373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

SN74LVC373AQPWREP 数据手册

数据手册 说明 数量 操作
SN74LVC373AQPWREP

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

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