您好,欢迎来到知芯网
  • 封装:20-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$3.895

更新日期:2024-04-01 00:04:00

产品简介:八路 D 类透明锁存器

查看详情
  • 封装:20-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$3.895

SN74BCT573DW 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN74BCT573DW 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 锁销
  • 系列:74BCT
  • 逻辑类型:D 型透明锁存器
  • 电路:8:8
  • 输出类型:三态
  • 电源电压:4.5 V ~ 5.5 V
  • 独立电路:1
  • 延迟时间 - 传输:6.1ns
  • 输出电流高,低:15mA,64mA
  • 工作温度:0°C ~ 70°C
  • 安装类型:表面贴装
  • 封装/外壳:20-SOIC(0.295",7.50mm 宽)
  • 供应商设备封装:20-SOIC
  • 包装:管件

产品特性

  • Operating Voltage Range of 4.5 V to 5.5 V
  • State-of-the-Art BiCMOS Design
  • Significantly Reduces ICCZ
  • Full Parallel Access for Loading
  • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

产品概述

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

SN74BCT573DW 数据手册

数据手册 说明 数量 操作
SN74BCT573DW

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

5 Pages页,74K 查看
SN74BCT573DWR

Octal D-Type Transparent Latches 20-SOIC 0 to 70

16页,667K 查看
SN74BCT573DWRE4

Octal D-Type Transparent Latches 20-SOIC 0 to 70

16页,667K 查看
SN74BCT573DWRG4

Octal D-Type Transparent Latches 20-SOIC 0 to 70

16页,667K 查看

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9