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SN74AS109AD

Texas Instruments 逻辑 - 触发器
  • 封装：16-SOIC（0.154"，3.90mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：管件
  • 参考价格：$2.1525

更新日期：2024-04-01 00:04:00

SN74AS109AD

Texas Instruments 逻辑 - 触发器

产品简介：具有清零和预设功能的双通道 J-K 上升沿触发器

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  • 封装：16-SOIC（0.154"，3.90mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：管件
  • 参考价格：$2.1525

SN74AS109AD 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN74AS109AD 中文资料属性参数

  • 标准包装：40
  • 类别：集成电路 (IC)
  • 家庭：逻辑 - 触发器
  • 系列：74AS
  • 功能：设置（预设）和复位
  • 类型：JK 型
  • 输出类型：差分
  • 元件数：2
  • 每个元件的位元数：1
  • 频率 - 时钟：105MHz
  • 延迟时间 - 传输：2.5ns
  • 触发器类型：正边沿
  • 输出电流高，低：2mA，20mA
  • 电源电压：4.5 V ~ 5.5 V
  • 工作温度：0°C ~ 70°C
  • 安装类型：表面贴装
  • 封装/外壳：16-SOIC（0.154"，3.90mm 宽）
  • 包装：管件
  • 其它名称：296-6331-5

产品特性

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

产品概述

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C. 
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SN74AS109AD 数据手册

数据手册 说明 数量 操作
SN74AS109AD

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

 9 Pages页,139K 查看
SN74AS109ADE4

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70

17页,684K 查看
SN74AS109ADG4

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70

17页,684K 查看
SN74AS109ADR

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

 9 Pages页,139K 查看
SN74AS109ADRE4

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the...

17页,684K 查看
SN74AS109ADRG4

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the...

17页,684K 查看

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