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  • 封装:56-BSSOP(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$2.666-$6.02

更新日期:2024-04-01 00:04:00

产品简介:具有三态输出的 9 位总线接口 D 类锁存器

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  • 封装:56-BSSOP(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$2.666-$6.02

SN74ALVCH16841DL 供应商

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  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
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  • 说明
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SN74ALVCH16841DL 中文资料属性参数

  • 标准包装:20
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 锁销
  • 系列:74ALVCH
  • 逻辑类型:D 型透明锁存器
  • 电路:10:10
  • 输出类型:三态
  • 电源电压:1.65 V ~ 3.6 V
  • 独立电路:2
  • 延迟时间 - 传输:1ns
  • 输出电流高,低:24mA,24mA
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 封装/外壳:56-BSSOP(0.295",7.50mm 宽)
  • 供应商设备封装:56-SSOP
  • 包装:管件
  • 其它名称:296-6266-5

产品特性

  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

产品概述

This 20-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVCH16841 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers.The SN74ALVCH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.OE\ does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16841 is characterized for operation from -40°C to 85°C.

SN74ALVCH16841DL 数据手册

数据手册 说明 数量 操作
SN74ALVCH16841DL

D-Type Transparent Latch 2 Channel 10:10 IC Tri-State 56-SSOP

15页,343K 查看

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