- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$2.232-$4.46
更新日期:2024-04-01 00:04:00
产品简介:具有三态输出的 3.3V 20 位总线接口触发器
查看详情- 封装:56-TFSOP(0.240",6.10mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$2.232-$4.46
SN74ALVCH16821DGGR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TSSOP-56
2022+ -
12000
-
上海市
-
-
-
原装可开发票
SN74ALVCH16821DGGR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 触发器
- 系列:74ALVCH
- 功能:标准
- 类型:D 型总线
- 输出类型:三态非反相
- 元件数:2
- 每个元件的位元数:10
- 频率 - 时钟:150MHz
- 延迟时间 - 传输:1ns
- 触发器类型:正边沿
- 输出电流高,低:24mA,24mA
- 电源电压:1.65 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-TFSOP(0.240",6.10mm 宽)
- 包装:®
- 其它名称:296-5249-6
产品特性
- Member of the Texas Instruments Widebus Family
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
This 20-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVCH16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
SN74ALVCH16821DGGR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
3.3-V 20-Bit Bus-Interface Flip-Flop with 3-State Outputs 56-TSSOP -40 to 85 |
12页,314K | 查看 |
![]() |
IC D-TYPE POS TRG DUAL 56TSSOP |
12页,314K | 查看 |
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