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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.52224-$1.43

更新日期:2024-04-01 00:04:00

产品简介:具有清零和预设功能的双通道 J-K 下降沿触发器

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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.52224-$1.43

SN74ALS112AN 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN74ALS112AN 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 触发器
  • 系列:74ALS
  • 功能:设置(预设)和复位
  • 类型:JK 型
  • 输出类型:差分
  • 元件数:2
  • 每个元件的位元数:1
  • 频率 - 时钟:30MHz
  • 延迟时间 - 传输:3ns
  • 触发器类型:负边沿
  • 输出电流高,低:400µA, 8mA
  • 电源电压:4.5 V ~ 5.5 V
  • 工作温度:0°C ~ 70°C
  • 安装类型:通孔
  • 封装/外壳:16-DIP(0.300",7.62mm)
  • 包装:管件
  • 其它名称:296-5013-5

产品特性

  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

产品概述

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C. 

SN74ALS112AN 数据手册

数据手册 说明 数量 操作
SN74ALS112AN

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70

16页,667K 查看
SN74ALS112AN

IC JK TYPE NEG TRG DUAL 16DIP

17页,1021K 查看
SN74ALS112AN3

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70

16页,667K 查看
SN74ALS112ANE4

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70

16页,667K 查看
SN74ALS112ANSR

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70

16页,667K 查看
SN74ALS112ANSR

IC JK TYPE NEG TRG DUAL 16SO

17页,1021K 查看
SN74ALS112ANSRE4

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70

16页,667K 查看
SN74ALS112ANSRG4

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70

16页,667K 查看

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