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更新日期:2024-04-01

产品简介:1Gbps 至 6.25Gbps 背板均衡器

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EQ50F100LR 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

EQ50F100LR 中文资料属性参数

  • 现有数量:0现货
  • 价格:停产
  • 系列:-
  • 包装:卷带(TR)剪切带(CT)? 得捷定制卷带
  • 产品状态:停产
  • 应用:数据传输
  • 接口:串行
  • 电压 - 供电:1.71V ~ 1.89V
  • 封装/外壳:6-WDFN 裸露焊盘
  • 供应商器件封装:6-WSON(3x3)
  • 安装类型:表面贴装型

产品特性

  • Recovers 6.25 Gbps signals after 30" of FR4
  • Single 1.8V power supply
  • Low power consumption: 85mW
  • Equalize up to 20dB loss at 2.5 GHz
  • 35 ps residual deterministic jitter at 5 Gbps
  • On-chip CML terminations
  • Small 3 mm x 3 mm 6-pin leadless LLP package

产品概述

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.

EQ50F100LR 数据手册

数据手册 说明 数量 操作
EQ50F100LR/NOPB

Data Transport Interface 6-WSON (3x3)

7页,237K 查看

EQ50F100LR 电路图

EQ50F100LR 电路图

EQ50F100LR 电路图

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