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CLVTH16373IDGGREP

Texas Instruments 逻辑 - 锁销
  • 封装：48-TFSOP（0.240"，6.10mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：Digi-Reel®
  • 参考价格：$1.341-$2.87

更新日期：2024-04-01 00:04:00

CLVTH16373IDGGREP

Texas Instruments 逻辑 - 锁销

产品简介：增强型产品，具有三态输出的 3.3V Abt 16 位透明 D 类锁存器

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  • 封装：48-TFSOP（0.240"，6.10mm 宽）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：Digi-Reel®
  • 参考价格：$1.341-$2.87

CLVTH16373IDGGREP 供应商

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CLVTH16373IDGGREP 中文资料属性参数

  • 标准包装：1
  • 类别：集成电路 (IC)
  • 家庭：逻辑 - 锁销
  • 系列：74LVTH
  • 逻辑类型：D 型透明锁存器
  • 电路：8:8
  • 输出类型：三态
  • 电源电压：2.7 V ~ 3.6 V
  • 独立电路：2
  • 延迟时间 - 传输：2.9ns
  • 输出电流高，低：32mA，64mA
  • 工作温度：-40°C ~ 85°C
  • 安装类型：表面贴装
  • 封装/外壳：48-TFSOP（0.240"，6.10mm 宽）
  • 供应商设备封装：48-TSSOP
  • 包装：®
  • 其它名称：296-22132-6

产品特性

  • Controlled Baseline One Assembly/Test Site, One Fabrication Site
  • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static- Power Dissipation
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up Tri-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High- Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22 4000-V Human Body Model (A114-A) 200-V Machine Model (A115-A)
  • 4000-V Human Body Model (A114-A)
  • 200-V Machine Model (A115-A)

产品概述

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
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CLVTH16373IDGGREP 电路图

CLVTH16373IDGGREP 电路图

CLVTH16373IDGGREP 电路图

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