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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.2244

更新日期:2024-04-01 00:04:00

产品简介:具有复位功能的高速 CMOS 逻辑四通道 D 类触发器

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  • 封装:16-DIP(0.300",7.62mm)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.2244

CD74HCT175EE4 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

CD74HCT175EE4 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 触发器
  • 系列:74HCT
  • 功能:主复位
  • 类型:D 型总线
  • 输出类型:差分
  • 元件数:1
  • 每个元件的位元数:4
  • 频率 - 时钟:25MHz
  • 延迟时间 - 传输:13ns
  • 触发器类型:正边沿
  • 输出电流高,低:4mA,4mA
  • 电源电压:4.5 V ~ 5.5 V
  • 工作温度:-55°C ~ 125°C
  • 安装类型:通孔
  • 封装/外壳:16-DIP(0.300",7.62mm)
  • 包装:管件

产品特性

  • Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
  • Positive Edge Pulse Triggering
  • Complementary Outputs
  • Buffered Inputs
  • Fanout (Over Temperature Range) Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

产品概述

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.

CD74HCT175EE4 数据手册

数据手册 说明 数量 操作
CD74HCT175EE4

High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

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