- 封装:14-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$0.517
更新日期:2024-04-01 00:04:00
产品简介:具有复位功能的高速 CMOS 逻辑双通道下降沿 J-K 触发器
查看详情- 封装:14-DIP(0.300",7.62mm)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$0.517
CD74HC107EE4 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
Texas Instruments
-
PDIP14
21+ -
200
-
上海市
-
-
-
一级代理原装
CD74HC107EE4 中文资料属性参数
- 标准包装:25
- 类别:集成电路 (IC)
- 家庭:逻辑 - 触发器
- 系列:74HC
- 功能:复位
- 类型:JK 型
- 输出类型:差分
- 元件数:2
- 每个元件的位元数:1
- 频率 - 时钟:35MHz
- 延迟时间 - 传输:14ns
- 触发器类型:负边沿
- 输出电流高,低:5.2mA,5.2mA
- 电源电压:2 V ~ 6 V
- 工作温度:-55°C ~ 125°C
- 安装类型:通孔
- 封装/外壳:14-DIP(0.300",7.62mm)
- 包装:管件
产品特性
- Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
- Asynchronous Reset
- Complementary Outputs
- Buffered Inputs
- Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range) Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il 1µA at VOL, VOH
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
产品概述
The HC107 and HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.The HCT logic family is functionally as well as pin compatible with the standard LS family.
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