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CD4044BEE4

Texas Instruments 逻辑 - 锁销
  • 封装：16-DIP（0.300"，7.62mm）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：管件
  • 参考价格：$0.1829

更新日期：2024-04-01 00:04:00

CD4044BEE4

Texas Instruments 逻辑 - 锁销

产品简介：具有三态输出的 CMOS 四路与非 R/S 锁存器

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  • 封装：16-DIP（0.300"，7.62mm）
  • RoHS：无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式：管件
  • 参考价格：$0.1829

CD4044BEE4 中文资料属性参数

  • 标准包装：25
  • 类别：集成电路 (IC)
  • 家庭：逻辑 - 锁销
  • 系列：4000B
  • 逻辑类型：S-R 锁存器
  • 电路：1:1
  • 输出类型：三态
  • 电源电压：3 V ~ 18 V
  • 独立电路：4
  • 延迟时间 - 传输：50ns
  • 输出电流高，低：6.8mA，6.8mA
  • 工作温度：-55°C ~ 125°C
  • 安装类型：通孔
  • 封装/外壳：16-DIP（0.300"，7.62mm）
  • 供应商设备封装：16-PDIP
  • 包装：管件

产品特性

  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications Holding register in multi-register system Four bits of independent storage with output ENABLE Strobed register General digital logic CD4043B for positive logic systems CD4044B for negative logic systems
  • Holding register in multi-register system
  • Four bits of independent storage with output ENABLE
  • Strobed register
  • General digital logic
  • CD4043B for positive logic systems
  • CD4044B for negative logic systems

产品概述

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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