- 封装:16-SOIC(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.196-$0.55
更新日期:2024-04-01
产品简介:CMOS 四路时钟控制“D”锁存器
查看详情- 封装:16-SOIC(0.209",5.30mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:Digi-Reel®
- 参考价格:$0.196-$0.55
CD4042BNSR 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
SO-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
CD4042BNSR 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 锁销
- 系列:4000B
- 逻辑类型:D 型透明锁存器
- 电路:1:1
- 输出类型:差分
- 电源电压:3 V ~ 18 V
- 独立电路:4
- 延迟时间 - 传输:40ns
- 输出电流高,低:6.8mA,6.8mA
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:16-SOIC(0.209",5.30mm 宽)
- 供应商设备封装:16-SO
- 包装:®
- 其它名称:296-29112-6
产品特性
- Clock polarity control
- Q and Q\ outputs
- Common Clock
- Low power TTL compatible
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- 5-V, 10-V, and 15-V parametric ratings
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices"
- Applications: Buffer storage Holding register General digital logic
- Buffer storage
- Holding register
- General digital logic
产品概述
CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4042BNSR 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
CMOS Quad Clocked "D" Latch |
12 Pages页,600K | 查看 |
![]() |
D-Type Transparent Latch 4 Channel 1:1 IC Differential 16-SO |
30页,1.83M | 查看 |
![]() |
CMOS Quad Clocked 'D' Latch 16-SO -55 to 125 |
15页,777K | 查看 |
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