VCBU3730GSCUS100_VCBU3730GSCUS100中文资料_价格

VCBU3730GSCUS100 供应商

公司
型号
品牌
封装/批号
数量
地区
日期
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询价

上海三崧电子有限公司 保2千
VCBU3730GSCUS100
TI
原厂原装
22+
3288
上海市
-
一级代理原装

安徽芯海技术有限公司
VCBU3730GSCUS100
TI
原厂原装
2318+
9200
合肥
-
科大讯飞战略投资企业

VCBU3730GSCUS100 中文资料属性参数

现有数量：0现货查看交期
价格：90 : ￥283.71611托盘
系列：TMS320DM37x, DaVinci?
包装：托盘
产品状态：在售
类型：数字媒体片内系统（DMSoC）
接口：1-Wire?，EBI/EMI，I2C，McBSP，McSPI，MMC/SD，UART，USB，USB OTG
时钟速率：1GHz
非易失性存储器：ROM（32kB）
片载 RAM：384kB
电压 - I/O：1.80V
电压 - 内核：1.10V
工作温度：0°C ~ 90°C（TJ）
安装类型：表面贴装型
封装/外壳：423-LFBGA，FCBGA
供应商器件封装：423-FCBGA（16x16）

产品特性

DM3730, DM3725 Digital Media Processors: Compatible with OMAP™ 3 Architecture ARM® microprocessor (MPU) Subsystem Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz NEON SIMD Coprocessor High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem Up to 800-MHz TMS320C64x+™ DSP Core Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) Video Hardware Accelerators POWER SGX™ Graphics Accelerator (DM3730 only) Tile Based Acrchitecture Delivering up to 20 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, Load Balancing, and Power Management Programmable High Quality Image Anti-Aliasing Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core Eight Highly Independent Functional Units Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation C64x+TM L1/L2 Memory Architecture
Compatible with OMAP™ 3 Architecture
ARM® microprocessor (MPU) Subsystem Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz NEON SIMD Coprocessor
Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz
NEON SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem Up to 800-MHz TMS320C64x+™ DSP Core Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) Video Hardware Accelerators
Up to 800-MHz TMS320C64x+™ DSP Core
Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
Video Hardware Accelerators
POWER SGX™ Graphics Accelerator (DM3730 only) Tile Based Acrchitecture Delivering up to 20 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, Load Balancing, and Power Management Programmable High Quality Image Anti-Aliasing
Tile Based Acrchitecture Delivering up to 20 MPoly/sec
Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load Balancing, and Power Management
Programmable High Quality Image Anti-Aliasing
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core Eight Highly Independent Functional Units Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation
Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle
Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle
Load-Store Architecture With Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements Protected Mode Operation Expectations Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Operation
Protected Mode Operation
Expectations Support for Error Detection and Program Redirection
Hardware Support for Modulo Loop Operation
C64x+TM L1/L2 Memory Architecture

产品概述

The DM37x generation of high-performance, applications processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption. This balance of performance and power allow the device to support the following example applications:The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded CE which are available directly from TI. Additionally, the device is fully backward compatible with previous Cortex™-A8 processors and OMAP™ processors.This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Applications Processor. The information contained in this data manual applies to both the commercial and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated. It consists of the following sections:

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