V62/08617-01XE

Texas Instruments 逻辑集成电路

RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Sgl Pos Edge Trgrd D-Type Flip-Flop

更新日期：2024-04-01 00:04:00

V62/08617-01XE

Texas Instruments 逻辑集成电路

产品简介：具有清零和预置端的单路正边沿触发式 D 型触发器（增强型产品）

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RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Sgl Pos Edge Trgrd D-Type Flip-Flop

V62/08617-01XE 中文资料属性参数

制造商：Texas Instruments
产品种类：触发器
电路数量：1
逻辑系列：LVC
逻辑类型：CMOS
极性：Inverting/Non-Inverting
输入类型：Single-Ended
输出类型：Differential
传播延迟时间：8.2 ns
高电平输出电流：- 24 mA
低电平输出电流：24 mA
Supply Voltage - Max：5.5 V
最大工作温度：+ 125 C
安装风格：SMD/SMT
封装 / 箱体：VSSOP
封装：Reel
最小工作温度：- 55 C
输入线路数量：1
输出线路数量：1
工厂包装数量：250
Supply Voltage - Min：1.65 V

产品特性

Controlled Baseline One Assembly Site One Test Site One Fabrication Site
One Assembly Site
One Test Site
One Fabrication Site
Extended Temperature Performance of –55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 7.9 ns at 3.3 V
Low Power Consumption, 10 µA Max ICC
±24 mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial Power Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)

产品概述

This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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