V62/06605-01XE

Texas Instruments 逻辑集成电路

RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Mil Enh Dual Pos Edge-Trgrd D-Type
参考价格：￥5.07-￥5.72

更新日期：2024-04-01 00:04:00

V62/06605-01XE

Texas Instruments 逻辑集成电路

产品简介：双通道正边沿触发式 D 型触发器（增强型产品）

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RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Mil Enh Dual Pos Edge-Trgrd D-Type
参考价格：￥5.07-￥5.72

V62/06605-01XE 中文资料属性参数

制造商：Texas Instruments
产品种类：触发器
电路数量：2
逻辑系列：LV
逻辑类型：CMOS
极性：Inverting/Non-Inverting
输入类型：Single-Ended
输出类型：Differential
传播延迟时间：20 ns
高电平输出电流：- 12 mA
低电平输出电流：12 mA
Supply Voltage - Max：5.5 V
最大工作温度：+ 125 C
安装风格：SMD/SMT
封装 / 箱体：TSSOP-14
封装：Reel
最小工作温度：- 55 C
输入线路数量：1
输出线路数量：1
工厂包装数量：2000
Supply Voltage - Min：2 V

产品特性

Controlled Baseline One Assembly/Test Site, One Fabrication Site
One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
2-V to 5.5-V VCC Operation
Max tpd of 13 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)

产品概述

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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