您好,欢迎来到知芯网
  • RoHS:
    • 镉(Cd)/镉化合物 0.01%
    • 六价隔(Cr6+)/六价隔化合物 0.10%
    • 铅(Pb)/铅化合物 0.10%
    • 汞(Hg)/汞化合物 0.10%
    • 多溴联苯(PBB)0.10%
    • 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
    说明:Gates (AND / NAND / OR / NOR) Mil Enh Dual 2-Inp Pos-NAND Gate
  • 参考价格:¥2.91-¥3.40

更新日期:2024-04-01

产品简介:增强型产品 2 通道、2 输入、1.65V 至 5.5V 与非门

查看详情
  • RoHS:
    • 镉(Cd)/镉化合物 0.01%
    • 六价隔(Cr6+)/六价隔化合物 0.10%
    • 铅(Pb)/铅化合物 0.10%
    • 汞(Hg)/汞化合物 0.10%
    • 多溴联苯(PBB)0.10%
    • 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
    说明:Gates (AND / NAND / OR / NOR) Mil Enh Dual 2-Inp Pos-NAND Gate
  • 参考价格:¥2.91-¥3.40

V62/05623-01XE 中文资料属性参数

  • 制造商:Texas Instruments
  • 产品种类:门(与/非与/或/非或)
  • 产品:NAND
  • 逻辑系列:LVC
  • 栅极数量:2
  • 线路数量(输入/输出):2 / 1
  • 高电平输出电流:- 32 mA
  • 低电平输出电流:32 mA
  • 传播延迟时间:5.3 ns
  • Supply Voltage - Max:5.5 V
  • Supply Voltage - Min:1.65 V
  • 最大工作温度:+ 115 C
  • 安装风格:SMD/SMT
  • 封装 / 箱体:SSOP-8
  • 封装:Reel
  • 最小工作温度:- 55 C
  • 输入线路数量:2
  • 输出线路数量:1
  • 工厂包装数量:3000

产品特性

  • Controlled Baseline One Assembly/Test Site, One Fabrication Site
  • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of -55°C to 115°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

产品概述

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC2G00W-EP performs the Boolean function Y = A • B or Y = A + B in positive logic.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9