V62/05621-01XE

Texas Instruments 逻辑集成电路

RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Mil Enh Sgl Pos Edge-Trgrd D-Type
参考价格：￥1.95-￥2.28

更新日期：2024-04-01

V62/05621-01XE

Texas Instruments 逻辑集成电路

产品简介：增强型产品单路上升沿 D 类触发器

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RoHS：
• 镉（Cd）/镉化合物 0.01%
• 六价隔（Cr6+）/六价隔化合物 0.10%
• 铅（Pb）/铅化合物 0.10%
• 汞（Hg）/汞化合物 0.10%
• 多溴联苯(PBB)0.10%
• 多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明：Flip Flops Mil Enh Sgl Pos Edge-Trgrd D-Type
参考价格：￥1.95-￥2.28

V62/05621-01XE 中文资料属性参数

制造商：Texas Instruments
产品种类：触发器
电路数量：1
逻辑系列：LVC
逻辑类型：CMOS
极性：Non-Inverting
输入类型：Single-Ended
输出类型：Single-Ended
传播延迟时间：5 ns
高电平输出电流：- 32 mA
低电平输出电流：32 mA
Supply Voltage - Max：5.5 V
最大工作温度：+ 115 C
安装风格：SMD/SMT
封装 / 箱体：SC-70
封装：Reel
最小工作温度：- 55 C
输入线路数量：1
输出线路数量：1
工厂包装数量：3000
Supply Voltage - Min：1.65 V

产品特性

Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range(1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C) Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability

产品概述

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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