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  • 参考价格:¥10.63-¥11.66

更新日期:2024-04-01 00:04:00

产品简介:具有三态输出的增强型产品 3.3V ABT 16 位寄存收发器

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  • 参考价格:¥10.63-¥11.66

V62/04715-01XE 中文资料属性参数

  • 制造商:Texas Instruments
  • 产品种类:总线收发器
  • 逻辑类型:BiCMOS
  • 逻辑系列:62
  • 每芯片的通道数量:16
  • 输入电平:LVTTL
  • 输出电平:LVTTL
  • 输出类型:3-State
  • 高电平输出电流:- 32 mA
  • 低电平输出电流:64 mA
  • 传播延迟时间:2.3 ns
  • Supply Voltage - Max:3.6 V
  • Supply Voltage - Min:2.7 V
  • 最大工作温度:+ 85 C
  • 封装 / 箱体:TSSOP-56
  • 封装:Reel
  • 功能:Latched Transceiver
  • 最小工作温度:- 40 C
  • 安装风格:SMD/SMT
  • 电路数量:2
  • 极性:Non-Inverting
  • 工厂包装数量:2000

产品特性

  • Controlled Baseline One Assembly/Test Site, One Fabrication Site
  • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product–Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State–of–the–Art Advanced BiCMOS Technology (ABT) Design for 3.3–V Operation and Low Static–Power Dissipation
  • Supports Mixed–Mode Signal Operation (5–V Input and Output Voltages With 3.3–V VCC)
  • Supports Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power–Up 3–State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C
  • Distributed VCC and GND Pins Minimize High–Speed Switching Noise
  • Flow–Through Architecture Optimizes PCB Layout
  • Latch–Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL–STD–883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

产品概述

The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCC operation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEAB or LEBA) and output–enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A–to–B latches are transparent; a subsequent low–to–high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs.Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.When VCC is between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.This device is fully specified for hot–insertion applications using Ioff and power–up 3–state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.

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