- 封装:100-TQFP
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:托盘
- 参考价格:$10.716-$19.65
更新日期:2024-04-01 00:04:00
产品简介:适用于电信、嵌入式和工业应用的 32 位 I/F、2kB FIFO 高性能 1394 3.3V 链路层
查看详情- 封装:100-TQFP
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:托盘
- 参考价格:$10.716-$19.65
TSB12LV01BPZT 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
TQFP-100(14x14)
2022+ -
12000
-
上海市
-
-
-
原装可开发票
-
TI
-
TQFP-100
新批号 -
887000
-
上海市
-
-
-
原厂发货进口原装微信同步QQ893727827
TSB12LV01BPZT 中文资料属性参数
- 视频文件:1394 Interface
- 标准包装:90
- 类别:集成电路 (IC)
- 家庭:接口 - 控制器
- 系列:-
- 控制器类型:连接层控制器
- 接口:IEEE 1394
- 电源电压:3.3V,5V
- 电流 - 电源:-
- 工作温度:-
- 安装类型:表面贴装
- 封装/外壳:100-TQFP
- 供应商设备封装:100-TQFP(14x14)
- 包装:托盘
- 其它名称:296-11062
产品特性
- Link Core Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus Transmits and Receives Correctly Formatted 1394 Packets Supports Asynchronous and Isochronous Data Transfers Performs Function of 1394 Cycle Master Generates and Checks 32-Bit CRC Detects Lost Cycle-Start Messages Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K Bytes
- Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus
- Transmits and Receives Correctly Formatted 1394 Packets
- Supports Asynchronous and Isochronous Data Transfers
- Performs Function of 1394 Cycle Master
- Generates and Checks 32-Bit CRC
- Detects Lost Cycle-Start Messages
- Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K Bytes
- Physical-Link Interface Compatible With Texas Instruments Physical Layer Devices (PHYs) Supports Transfer Speeds of 100, 200, and 400 Mbits/s Timing Compliant with IEEE 1394a2000
- Compatible With Texas Instruments Physical Layer Devices (PHYs)
- Supports Transfer Speeds of 100, 200, and 400 Mbits/s
- Timing Compliant with IEEE 1394a2000
- Host Bus Interface Provides Chip Control With Directly Addressable Registers Is Interrupt Driven to Minimize Host Polling Has a Generic 32-Bit Host Bus Interface
- Provides Chip Control With Directly Addressable Registers
- Is Interrupt Driven to Minimize Host Polling
- Has a Generic 32-Bit Host Bus Interface
- General Operates From a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs Manufactured With Low-Power CMOS Technology 100-Pin PZT Package for 0°C to 70°C and 40°C to 85°C (I Temperature) Operation
- Operates From a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs
- Manufactured With Low-Power CMOS Technology
- 100-Pin PZT Package for 0°C to 70°C and 40°C to 85°C (I Temperature) Operation
产品概述
The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below.All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made:However, there are three restrictions that were not present in the TSB12LV01A device:This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus.
TSB12LV01BPZT 数据手册
| 数据手册 | 说明 | 数量 | 操作 |
|---|---|---|---|
TSB12LV01BPZT
|
IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
77 Pages页,439K | 查看 |
TSB12LV01BPZT
|
IEEE 1394 Link Layer Controller IEEE 1394-1995, 1394a-2000 Parallel Interface 100-TQFP (14x14) |
5页,85K | 查看 |
TSB12LV01BPZTG4
|
High Performance 1394 3.3V Link Layer for Telecom, Embedded & Industrial App.,32-Bit I/F, 2kb FIFO 100-TQFP 0 to 70 |
5页,85K | 查看 |
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