TMS320VC5402PGE100

标准包装：60
类别：集成电路 (IC)
家庭：嵌入式 - DSP（数字式信号处理器）
系列：TMS320C54x
类型：定点
接口：主机接口，McBSP
时钟速率：100MHz
非易失内存：ROM（8 kB）
芯片上RAM：32kB
电压 - 输入/输出：3.30V
电压 - 核心：1.80V
工作温度：-40°C ~ 100°C
安装类型：表面贴装
封装/外壳：144-LQFP
供应商设备封装：144-LQFP（20x20）
包装：托盘
配用：296-31413-ND - XDS560 CLASS HIGH SPEED EMULATOR296-23043-ND - BLACKHAWK XDS560 USB EMULATOR296-15829-ND - DSP STARTER KIT FOR TMS320C5416
其它名称：296-10762296-10762-5296-10762-5-ND

产品特性

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals Software-Programmable Wait-State Generator and Programmable Bank Switching On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source Two Multichannel Buffered Serial Ports (McBSPs) Enhanced 8-Bit Parallel Host-Port Interface (HPI8) Two 16-Bit Timers Six-Channel Direct Memory Access (DMA) Controller
Software-Programmable Wait-State Generator and Programmable Bank Switching
On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
Two Multichannel Buffered Serial Ports (McBSPs)
Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
Two 16-Bit Timers
Six-Channel Direct Memory Access (DMA) Controller
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

产品概述

The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the '5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

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TMS320VC5402PGE100 数据手册

数据手册	说明	数量	操作
TMS320VC5402PGE100	FIXED-POINT DIGITAL SIGNAL PROCESSOR	68 Pages页,939K	查看

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