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TMS320C6743DPTP3

Texas Instruments DSP（数字信号处理器）

更新日期：2024-04-01 00:04:00

TMS320C6743DPTP3

Texas Instruments DSP（数字信号处理器）

产品简介：低功耗 C674x 浮点 DSP- 375MHz

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TMS320C6743DPTP3 供应商

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TMS320C6743DPTP3 中文资料属性参数

  • 现有数量：0现货查看交期
  • 价格：40 : ￥111.10000托盘
  • 系列：TMS320C674x
  • 包装：托盘
  • 产品状态：在售
  • 类型：定点/浮点
  • 接口：EBI/EMI，以太网 MAC，I2C，McASP，SPI，UART
  • 时钟速率：375MHz
  • 非易失性存储器：外部
  • 片载 RAM：320kB
  • 电压 - I/O：3.30V
  • 电压 - 内核：1.20V
  • 工作温度：0°C ~ 90°C（TJ）
  • 安装类型：表面贴装型
  • 封装/外壳：176-LQFP 裸露焊盘
  • 供应商器件封装：176-HLQFP（24x24）

产品特性

  • Applications Networking High-Speed Encoding Professional Audio™
  • Networking
  • High-Speed Encoding
  • Professional Audio™
  • Software Support TI DSP/BIOS™ Chip Support Library and DSP Library
  • TI DSP/BIOS™
  • Chip Support Library and DSP Library
  • 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core Load-Store Architecture with Nonaligned Support 64 General-Purpose Registers (32-Bit)Six ALU (32- and 40-Bit) Functional Units Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle Two Multiply Functional Units Mixed-Precision IEEE Floating Point Multiply Supported up to: 2 SP x SP -> SP Per Clock 2 SP x SP -> DP Every Two Clocks 2 SP x DP -> DP Every Three Clocks 2 DP x DP -> DP Every Four Clocks Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples Instruction Packing Reduces Code Size All Instructions Conditional Hardware Support for Modulo Loop Operation Protected Mode Operation Exceptions Support for Error Detection and Program Redirection
  • Load-Store Architecture with Nonaligned Support
  • 64 General-Purpose Registers (32-Bit)
  • Six ALU (32- and 40-Bit) Functional Units Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Two Multiply Functional Units Mixed-Precision IEEE Floating Point Multiply Supported up to: 2 SP x SP -> SP Per Clock 2 SP x SP -> DP Every Two Clocks 2 SP x DP -> DP Every Three Clocks 2 DP x DP -> DP Every Four Clocks Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Mixed-Precision IEEE Floating Point Multiply Supported up to: 2 SP x SP -> SP Per Clock 2 SP x SP -> DP Every Two Clocks 2 SP x DP -> DP Every Three Clocks 2 DP x DP -> DP Every Four Clocks
  • 2 SP x SP -> SP Per Clock
  • 2 SP x SP -> DP Every Two Clocks
  • 2 SP x DP -> DP Every Three Clocks
  • 2 DP x DP -> DP Every Four Clocks
  • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Hardware Support for Modulo Loop Operation
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
  • C674x Instruction Set Features Superset of the C67x+ and C64x+ ISAs 3000 MIPS and 2250 MFLOPS C674x Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting Compact 16-Bit Instructions
  • Superset of the C67x+ and C64x+ ISAs
  • 3000 MIPS and 2250 MFLOPS C674x
  • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture 32KB of L1P Program RAM/Cache 32KB of L1D Data RAM/Cache 128KB of L2 Unified Mapped RAM/Cache Flexible RAM/Cache Partition (L1 and L2)
  • 32KB of L1P Program RAM/Cache
  • 32KB of L1D Data RAM/Cache
  • 128KB of L2 Unified Mapped RAM/Cache
  • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3): 2 Transfer Controllers 32 Independent DMA Channels 8 Quick DMA Channels Programmable Transfer Burst Size
  • 2 Transfer Controllers
  • 32 Independent DMA Channels
  • 8 Quick DMA Channels
  • Programmable Transfer Burst Size
  • 3.3-V LVCMOS I/Os
  • Two External Memory Interfaces: EMIFA NOR (8-Bit-Wide Data) NAND (8-Bit-Wide Data) EMIFB 16-bit SDRAM, up to 128MB
  • EMIFA NOR (8-Bit-Wide Data) NAND (8-Bit-Wide Data)
  • NOR (8-Bit-Wide Data)
  • NAND (8-Bit-Wide Data)
  • EMIFB 16-bit SDRAM, up to 128MB
  • 16-bit SDRAM, up to 128MB
  • Two Configurable 16550-Type UART Modules: UART0 with Modem Control Signals 16-Byte FIFO 16x or 13x Oversampling Option
  • UART0 with Modem Control Signals
  • 16-Byte FIFO
  • 16x or 13x Oversampling Option
  • One Serial Peripheral Interface (SPI) with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • Programmable Real-Time Unit Subsystem (PRUSS) Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled Through Software to Save Power Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain Dedicated Interrupt Controller Dedicated Switched Central Resource
  • Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM per Core 512 Bytes of Data RAM per Core PRUSS can be Disabled Through Software to Save Power Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
  • 32-Bit Load-Store RISC Architecture
  • 4KB of Instruction RAM per Core
  • 512 Bytes of Data RAM per Core
  • PRUSS can be Disabled Through Software to Save Power
  • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
  • Standard Power-Management Mechanism Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain
  • Clock Gating
  • Entire Subsystem Under a Single PSC Clock Gating Domain
  • Dedicated Interrupt Controller
  • Dedicated Switched Central Resource
  • Two Multichannel Audio Serial Ports (McASPs): Supports TDM, I2S, and Similar Formats FIFO Buffers for Transmit and Receive
  • Supports TDM, I2S, and Similar Formats
  • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps RMII Ethernet Media Access Controller (EMAC): IEEE 802.3 Compliant (3.3-V I/O Only) RMII Media-Independent Interface Management Data I/O (MDIO) Module
  • IEEE 802.3 Compliant (3.3-V I/O Only)
  • RMII Media-Independent Interface
  • Management Data I/O (MDIO) Module
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs): Dedicated 16-Bit Time-Base Counter with Period and Frequency Control 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs Dead-Band Generation PWM Chopping by High-Frequency Carrier Trip Zone Input
  • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
  • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
  • Dead-Band Generation
  • PWM Chopping by High-Frequency Carrier
  • Trip Zone Input
  • Three 32-Bit Event Capture (eCAP) Modules: Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs Single-Shot Capture of up to Four Event Time-Stamps
  • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
  • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
  • Commercial or Automotive Temperature

产品概述

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
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TMS320C6743DPTP3 电路图

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