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  • 封装:272-BBGA
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:托盘
  • 参考价格:$16.02-$26.7

更新日期:2024-04-01 00:04:00

产品简介:C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA

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  • 封装:272-BBGA
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:托盘
  • 参考价格:$16.02-$26.7

TMS320C6712DZDP150 供应商

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TMS320C6712DZDP150 中文资料属性参数

  • 标准包装:40
  • 类别:集成电路 (IC)
  • 家庭:嵌入式 - DSP(数字式信号处理器)
  • 系列:TMS320C67x
  • 类型:浮点
  • 接口:McBSP
  • 时钟速率:150MHz
  • 非易失内存:外部
  • 芯片上RAM:72kB
  • 电压 - 输入/输出:3.30V
  • 电压 - 核心:1.26V
  • 工作温度:0°C ~ 90°C
  • 安装类型:表面贴装
  • 封装/外壳:272-BBGA
  • 供应商设备封装:272-BGA(27x27)
  • 包装:托盘
  • 配用:296-31413-ND - XDS560 CLASS HIGH SPEED EMULATOR296-23043-ND - BLACKHAWK XDS560 USB EMULATOR296-15831-ND - DSP STARTER KIT FOR TMS320C6713
  • 其它名称:296-19390

产品特性

  • Low-Price/High-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6712D Eight 32-Bit Instructions/Cycle 150-MHz Clock Rate 6.7-ns Instruction Cycle Time 900 MFLOPS
  • Eight 32-Bit Instructions/Cycle
  • 150-MHz Clock Rate
  • 6.7-ns Instruction Cycle Time
  • 900 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional
  • Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point)
  • Four ALUs (Floating- and Fixed-Point)
  • Two ALUs (Fixed-Point)
  • Two Multipliers (Floating- and Fixed-Point)
  • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Instruction Set Features Hardware Support for IEEE Single-Precision and Double-Precision Instructions Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization
  • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
  • Byte-Addressable (8-, 16-, 32-Bit Data)
  • 8-Bit Overflow Protection
  • Saturation
  • Bit-Field Extract, Set, Clear
  • Bit-Counting
  • Normalization
  • L1/L2 Memory Architecture 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
  • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
  • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration Boot Mode: 8- and 16-Bit ROM Boot Little Endian, Big Endian
  • Boot Mode: 8- and 16-Bit ROM Boot
  • Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit External Memory Interface (EMIF) Glueless Interface to Asynchronous Memories: SRAM and EPROM Glueless Interface to Synchronous Memories: SDRAM and SBSRAM 256M-Byte Total Addressable External Memory Space
  • Glueless Interface to Asynchronous Memories: SRAM and EPROM
  • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
  • 256M-Byte Total Addressable External Memory Space
  • Two Multichannel Buffered Serial Ports (McBSPs) Direct Interface to T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible Up to 256 Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Direct Interface to T1/E1, MVIP, SCSA Framers
  • ST-Bus-Switching Compatible
  • Up to 256 Channels Each
  • AC97-Compatible
  • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software-Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix)
  • CMOS Technology 0.13-µm/6-Level Copper Metal Process
  • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/Os, 1.20-V Internal

产品概述

The TMS320C67x™ DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices) are members of the floating-point DSP family in the TMS320C6000. DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6712D device is the lowest-cost DSP in the C6000™ DSP platform. The C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712D can produce two MACs per cycle for a total of 300 MMACS.The C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712D device also includes a dedicated general-purpose input/output (GPIO) peripheral module.The C6712D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.The C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

TMS320C6712DZDP150 数据手册

数据手册 说明 数量 操作
TMS320C6712DZDP150

Floating-Point Digital Signal Processors 272-BGA

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TMS320C6712DZDP150 电路图

TMS320C6712DZDP150 电路图

TMS320C6712DZDP150 电路图

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