- 封装:16-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$10.38-$19.03
更新日期:2024-04-01
产品简介:四路 PECL 线路接收器
查看详情- 封装:16-SOIC(0.154",3.90mm 宽)
- RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
- 包装方式:管件
- 参考价格:$10.38-$19.03
TB5R2D 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI(德州仪器)
-
SOIC-16
2022+ -
12000
-
上海市
-
-
-
原装可开发票
-
TI
-
射频接收器
21+ -
3000
-
上海市
-
-
-
原装现货,品质为先,请来电垂询!
-
TI/德州仪器
-
-
21+ -
90000
-
上海市
-
-
-
TI
-
TSSOP
23+ -
46000
-
合肥
-
-
-
科大讯飞战略投资企业,提供一站式配套服务
TB5R2D 中文资料属性参数
- 标准包装:40
- 类别:集成电路 (IC)
- 家庭:接口 - 驱动器,接收器,收发器
- 系列:-
- 类型:接收器
- 驱动器/接收器数:0/4
- 规程:-
- 电源电压:4.5 V ~ 5.5 V
- 安装类型:表面贴装
- 封装/外壳:16-SOIC(0.154",3.90mm 宽)
- 供应商设备封装:16-SOIC N
- 包装:管件
- 其它名称:296-15949-5
产品特性
- Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
- Pin Equivalent to General Trade 26LS32
- High Input Impedance Approximately 8 k
- 4-ns Maximum Propagation Delay
- TB5R1 Provides 50-mV Hysteresis
- TB5R2 With -125-mV Threshold Offset for Preferred State Output
- -1.1-V to 7.1-V Common Mode Range
- Single 5-V ±10% Supply
- Slew Rate Limited (1 ns min 80% to 20%)
- TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
- ESD Protection HBM > 3 kV, CDM > 2 kV
- Operating Temperature Range: -40°C to 85°C
- Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
- APPLICATIONS Digital Data or Clock Transmission Over Balanced Lines
- Digital Data or Clock Transmission Over Balanced Lines
产品概述
These quad differential receivers accept digital data over
balanced transmission lines. They translate differential input logic levels to
TTL output logic levels.The TB5R1 is a pin- and function-compatible replacement for
the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD
protection.The TB5R2 is a pin- and function-compatible replacement for
the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input
offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2
preferred state feature places the high state when the inputs are open, shorted
to ground, or shorted to the power supply.The power-down loading characteristics of the receiver input
circuit are approximately 8 k relative to the power supplies; hence
they do not load the transmission line when the circuit is powered down.The packaging for these differential line receivers include
a 16-pin gull wing SOIC (DW) and SOIC (D).The enable inputs of this device include internal pullup
resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs
are open circuited.
TB5R2D 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
![]() |
QUAD DIFFERENTIAL PECL RECEIVERS |
11 Pages页,328K | 查看 |
![]() |
0/4 Receiver 16-SOIC |
16页,906K | 查看 |
![]() |
Quad PECL Line Receiver 16-SOIC -40 to 85 |
14页,524K | 查看 |
![]() |
Quad PECL Line Receiver 16-SOIC -40 to 85 |
14页,524K | 查看 |
![]() |
QUAD DIFFERENTIAL PECL RECEIVERS |
11 Pages页,328K | 查看 |
![]() |
0/4 Receiver 16-SOIC |
16页,906K | 查看 |
![]() |
Quad PECL Line Receiver 16-SOIC -40 to 85 |
14页,524K | 查看 |
![]() |
Quad PECL Line Receiver 16-SOIC -40 to 85 |
14页,524K | 查看 |
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