您好,欢迎来到知芯网

更新日期:2024-04-01 00:04:00

产品简介:具有输出寄存器和多路复用三态输出的同步加/减计数器

查看详情

SNJ54LS697J 中文资料属性参数

  • 现有数量:0现货2,411Factory
  • 价格:在售
  • 系列:*
  • 包装:管件
  • 产品状态:在售
  • 逻辑类型:-
  • 方向:-
  • 元件数:-
  • 每个元件位数:-
  • 复位:-
  • 定时:-
  • 计数速率:-
  • 触发器类型:-
  • 电压 - 供电:-
  • 工作温度:-
  • 安装类型:-
  • 封装/外壳:-
  • 供应商器件封装:-

产品特性

  • 4-Bit Counters/Registers
  • Multiplexed Outputs for Counter or Latched Data
  • 3-State Outputs Drive Bus Lines Directly
  • 'LS696 … Decade Counter, Direct Clear'LS697…Binary Counter, Direct Clear'LS699…Binary Counter, Synchronous Clear

产品概述

These low-power Schottky LSI devices incorporate synchronous up/down counters, four-bit D-type registers, and quadruple two-line to one-line multiplexers with three state outputs in a single 20-pin package. The up/down counters are programmable from the data inputs and feature enable P\ and enable T\ and a ripple-carry output for easy expansion. The register/counter select input R/C\, selects the counter when low and the register when high for the three-state outputs, QA, QB, QC, and QD. These outputs are rated at 12 and 24 milliamperes (54LS/74LS) for good bus driving performance. Both the counter CCK and register clock RCK are positive-edge triggered. The counter clear CCLR\ is active low and is asynchronous on the 'LS696 and 'LS697, synchronous on the 'LS699. Loading of the counter is accomplished when LOAD\ is taken low and a positive transition occurs on the counter clock CCK. Expansion is easily accomplished by connecting RCO\ of the first stage to ENT\ of the second stage, etc. All ENP\ inputs can be tied common and used as a master enable or disable control.  

IC 索引: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9