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  • 封装:20-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.40576-$1.11

更新日期:2024-04-01 00:04:00

产品简介:具有总线保持、TTL 兼容型 CMOS 输入和三态输出的 8 通道、2.7V 至 3.6V 反相器

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  • 封装:20-SOIC(0.295",7.50mm 宽)
  • RoHS:无铅 / 符合限制有害物质指令(RoHS)规范要求
  • 包装方式:管件
  • 参考价格:$0.40576-$1.11

SN74LVTH240DW 供应商

  • 公司
  • 型号
  • 品牌
  • 封装/批号
  • 数量
  • 地区
  • 日期
  • 说明
  • 询价

SN74LVTH240DW 中文资料属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 栅极和逆变器
  • 系列:74LVTH
  • 逻辑类型:逆变器,缓冲器
  • 电路数:2
  • 输入数:4
  • 特点:三态
  • 电源电压:2.7 V ~ 3.6 V
  • 电流 - 静态(最大值):5mA
  • 输出电流高,低:32mA,64mA
  • 逻辑电平 - 低:0.8V
  • 逻辑电平 - 高:2V
  • 额定电压和最大 CL 时的最大传播延迟:2.6ns @ 3.3V,50pF
  • 工作温度:-40°C ~ 85°C
  • 安装类型:表面贴装
  • 供应商设备封装:20-SOIC
  • 封装/外壳:20-SOIC(0.295",7.50mm 宽)
  • 包装:管件
  • 其它名称:296-34091-5SN74LVTH240DW-ND

产品特性

  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

产品概述

These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the devices pass data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

SN74LVTH240DW 数据手册

数据手册 说明 数量 操作
SN74LVTH240DW

Buffer, Inverting 2 Element 4 Bit per Element Push-Pull Output 20-SOIC

24页,1.33M 查看
SN74LVTH240DWR

3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

18 Pages页,418K 查看
SN74LVTH240DWR

Buffer, Inverting 2 Element 4 Bit per Element Push-Pull Output 20-SOIC

24页,1.33M 查看

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