- RoHS:
镉(Cd)/镉化合物 0.01%
六价隔(Cr6+)/六价隔化合物 0.10%
铅(Pb)/铅化合物 0.10%
汞(Hg)/汞化合物 0.10%
多溴联苯(PBB)0.10%
多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明:Gates (AND / NAND / OR / NOR) EP Dual 2-Inp Pos- Nor Gate - 参考价格:¥3.11-¥3.29
更新日期:2024-04-01 00:04:00
产品简介:增强型产品 2 通道、2 输入、1.65V 至 5.5V 或非门
查看详情- RoHS:
镉(Cd)/镉化合物 0.01%
六价隔(Cr6+)/六价隔化合物 0.10%
铅(Pb)/铅化合物 0.10%
汞(Hg)/汞化合物 0.10%
多溴联苯(PBB)0.10%
多溴联苯醚(PBDE)0.10% - 含十溴二苯醚(Deca-BDE) 0.10%
说明:Gates (AND / NAND / OR / NOR) EP Dual 2-Inp Pos- Nor Gate - 参考价格:¥3.11-¥3.29
SN74LVC2G02MDCUREP 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
-
TI
-
TSSOP
23+ -
46000
-
合肥
-
-
-
科大讯飞战略投资企业,提供一站式配套服务
SN74LVC2G02MDCUREP 中文资料属性参数
- 制造商:Texas Instruments
- 产品种类:门(与/非与/或/非或)
- 产品:NOR
- 逻辑系列:LVC
- 栅极数量:Dual
- 线路数量(输入/输出):2 / 1
- 高电平输出电流:- 24 mA
- 低电平输出电流:24 mA
- 传播延迟时间:5.9 ns
- Supply Voltage - Max:5.5 V
- Supply Voltage - Min:1.65 V
- 最大工作温度:+ 85 C
- 安装风格:SMD/SMT
- 封装 / 箱体:VSSOP-8
- 封装:Reel
- 最小工作温度:- 55 C
- 输入线路数量:2
- 输出线路数量:1
- 工厂包装数量:3000
产品特性
- Controlled BaselineOne Assembly SiteOne Test SiteOne Fabrication Site
- One Assembly Site
- One Test Site
- One Fabrication Site
- Extended Temperature Performance of -55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product Change Notification
- Qualification Pedigree(1)
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.9 ns at 3.3 V
- Low Power Consumption, 10 µA Max ICC
- ±24 mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
产品概述
This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC2G02 performs the Boolean function Y = A + B or Y = AB in positive logic.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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