SN74LVC1G125DPWR_SN74LVC1G125DPWR中文资料_价格

SN74LVC1G125DPWR 供应商

公司
型号
品牌
封装/批号
数量
地区
日期
说明
询价

上海三崧电子有限公司 保2千
SN74LVC1G125DPWR
TI
原厂原装
22+
3288
上海市
-
一级代理原装

深圳市讯运电子有限公司
SN74LVC1G125DPWR
TI(德州仪器)
X2SON-4(0.8x0.8)
2022+
12000
上海市
-
原装可开发票

上海德懿电子科技有限公司
SN74LVC1G125DPWR
TI
-
21+
10000
上海市
-
原装现货，品质为先，请来电垂询！

苏州迅昊科技有限公司
SN74LVC1G125DPWR
TI
-
2021+
28000
苏州
-

SN74LVC1G125DPWR 中文资料属性参数

现有数量：57,263现货9,000Factory
价格：1 : ￥3.18000剪切带（CT）3,000 : ￥1.13366卷带（TR）
系列：74LVC
包装：卷带（TR）剪切带（CT）? 得捷定制卷带
产品状态：在售
逻辑类型：-
电路数：-
输入数：-
特性：-
电压 - 供电：-
电流 - 静态（最大值）：-
电流 - 输出高、低：-
逻辑电平 - 低：-
逻辑电平 - 高：-
不同 V、最大 CL 时最大传播延迟：-
工作温度：-
安装类型：表面贴装型
供应商器件封装：4-X2SON（0.8x0.8）
封装/外壳：4-XFDFN 裸露焊盘

产品特性

Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to VCC
Max tpd of 3.7 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)

产品概述

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

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SN74LVC1G125DPWR 数据手册

数据手册	说明	数量	操作
SN74LVC1G125DPWR	Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G125 SCES223T–APRIL 1999–REVISED OCTOBER 2014 SN74LVC1G125 Single Bus Buffer Gate With 3-State Output 1 Features 3 Description This bus buffer gate is designed for 1.65-V to 5.5-V 1? Available in the Ultra Small 0.64-mm 2 V CC operation. Package (DPW) With 0.5-mm Pitch The SN74LVC1G125 device is a single line driver ? Supports 5-V V CC Operation with a 3-state output. The output is disabled when the ? Inputs Accept Voltages to 5.5 V output-enable (OE) input is high. ? Provides Down Translation to V CC The CMOS device has high output drive while ? Max t pd of 3.7 ns at 3.3 V maintaining low static power dissipation over a broad ? Low Power Consumption, 10- μA Max I CC V CC operating range. ? ±24-mA Output Drive at 3.3 V The SN74LVC1G125 device is available in a variety ? I off Supports Live Insertion, Partial-Power-Down of packages including the ultra-small DPW package Mode, and Back-Drive Prote	37页,1.73M	查看
SN74LVC1G125DPWR_1298	Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G125 SCES223T–APRIL 1999–REVISED OCTOBER 2014 SN74LVC1G125 Single Bus Buffer Gate With 3-State Output 1 Features 3 Description This bus buffer gate is designed for 1.65-V to 5.5-V 1? Available in the Ultra Small 0.64-mm 2 V CC operation. Package (DPW) With 0.5-mm Pitch The SN74LVC1G125 device is a single line driver ? Supports 5-V V CC Operation with a 3-state output. The output is disabled when the ? Inputs Accept Voltages to 5.5 V output-enable (OE) input is high. ? Provides Down Translation to V CC The CMOS device has high output drive while ? Max t pd of 3.7 ns at 3.3 V maintaining low static power dissipation over a broad ? Low Power Consumption, 10- μA Max I CC V CC operating range. ? ±24-mA Output Drive at 3.3 V The SN74LVC1G125 device is available in a variety ? I off Supports Live Insertion, Partial-Power-Down of packages including the ultra-small DPW package Mode, and Back-Drive Prote	37页,1.73M	查看

SN74LVC1G125DPWR