- 封装:20-TSSOP(0.173",4.40mm 宽)
- RoHS:库存产品核实请求 / 库存产品核实请求
- 包装方式:Digi-Reel®
- 参考价格:$2.16-$4.32
更新日期:2024-04-01 00:04:00
产品简介:增强型产品,具有三态输出寄存器的双路 16 位二进制计数器
查看详情- 封装:20-TSSOP(0.173",4.40mm 宽)
- RoHS:库存产品核实请求 / 库存产品核实请求
- 包装方式:Digi-Reel®
- 参考价格:$2.16-$4.32
SN74LV8154MPWREP 供应商
- 公司
- 型号
- 品牌
- 封装/批号
- 数量
- 地区
- 日期
- 说明
- 询价
-
TI
-
原厂原装
22+ -
3288
-
上海市
-
-
-
一级代理原装
SN74LV8154MPWREP 中文资料属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 -计数器,除法器
- 系列:74LV
- 逻辑类型:二进制计数器
- 方向:上
- 元件数:2
- 每个元件的位元数:16
- 复位:-
- 计时:-
- 计数速率:25MHz
- 触发器类型:正边沿
- 电源电压:2 V ~ 5.5 V
- 工作温度:-55°C ~ 125°C
- 安装类型:表面贴装
- 封装/外壳:20-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:20-TSSOP
- 包装:®
- 其它名称:296-22578-6
产品特性
- Controlled Baseline One Assembly Site One Test Site One Fabrication Site
- One Assembly Site
- One Test Site
- One Fabrication Site
- Extended Temperature Performance of -55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
- 2-V to 5.5-V VCC Operation
- Max tpd of 25 ns at 5 V (RCLK to Y)
- Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
SN74LV8154MPWREP 数据手册
数据手册 | 说明 | 数量 | 操作 |
---|---|---|---|
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Counter IC Binary Counter 2 Element 16 Bit Positive Edge 20-TSSOP |
15页,561K | 查看 |
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